pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL: Parser, Dataflow Analyzer, Controlflow Analyzer and Code Generator

Installation

In a virtualenv (see these instructions if you need to create one):

pip3 install pyverilog

Releases

Version Released Bullseye
Python 3.9
Bookworm
Python 3.11
Files
1.3.0 2020-12-30  
1.2.1 2020-05-03  
1.2.0 2019-11-19  
1.1.4 2019-03-30  
1.1.3 2018-11-25  
1.1.2 2018-07-01  
1.1.1 2017-10-04  
1.1.0 2017-10-01  
1.0.9 2017-05-02  
1.0.8 2017-04-10  
1.0.7 2017-04-07  
1.0.6 2016-01-21  
1.0.5 2016-01-18  
1.0.4 2015-11-22  
1.0.3 2015-11-21  
1.0.2 2015-11-19  
1.0.1 2015-10-31  
1.0.0 2015-10-29  
0.9.6 2015-08-18  
0.9.5 2015-06-21  
0.9.3 2015-05-23  
0.9.2 2015-02-07  
0.9.1 2014-11-10  

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Page last updated 2025-07-18 04:25:21 UTC